Alibaba’s Damo Academy Unveils XuanTie C950, Pushing RISC-V Into Server-Class AI Computing

Alibaba Group Holding’s Damo Academy launched its flagship XuanTie C950 CPU in Shanghai on March 24, setting a new RISC-V performance mark and signaling that the open instruction-set architecture is moving from edge devices into server-class AI workloads—an inflection that could reshape China’s chip supply chain and cloud procurement in 2026.

The company said the C950 is the first RISC-V CPU able to benchmark against mainstream server products, addressing the two constraints that kept RISC-V out of high-end computing: single-core performance and software ecosystem friction. Early user testing highlighted by Nick Brown, a senior researcher at the University of Edinburgh, reinforced the positioning as “server-grade,” according to remarks delivered at the event.

Market attention is now shifting from the novelty of a record score to what it implies for deployment: whether Chinese cloud operators and systems integrators can adopt RISC-V platforms at scale for AI agents and model inference without paying licensing fees embedded in proprietary architectures.

Breaking Benchmark Barriers Shifts RISC-V’s Competitive Set

Damo Academy said the XuanTie C950 surpassed 70 points in the SPECint2006 single-core benchmark, a threshold it framed as a first for RISC-V in general-purpose performance. For investors and procurement teams, that claim matters less as a headline number than as evidence that RISC-V can compete in CPU-heavy layers of AI infrastructure—web services, databases and encryption—where accelerators alone do not solve bottlenecks.

In cloud workload tests including MySQL, Redis, Nginx and OpenSSL, Damo Academy said hardware-software co-optimization put C950 in the industry’s top tier. It added that cloud networking and storage performance improved by more than 30% versus some mainstream products, a datapoint likely to be scrutinized by hyperscalers as they attempt to reduce total cost of ownership under rising AI traffic.

Bundling Native AI Engines Pulls RISC-V Toward Model Deployment

Alongside the CPU, Damo Academy introduced two RISC-V native AI engines—a Vector acceleration engine and a Matrix acceleration engine—mapped under a unified addressing model with XuanTie processors. The company said the design targets tighter coupling between general-purpose compute and AI compute, positioning RISC-V not just as a low-cost CPU option but as a controllable platform for model-serving stacks.

Damo Academy said the engines natively support running large models such as Qwen3 and DeepSeek V3. The strategic read-through for the supply chain is that RISC-V’s “openness” is being packaged into a deployment argument: faster customization for specific inference patterns, and fewer licensing constraints when building CPU-plus-AI silicon for domestic cloud and enterprise environments.

Scaling From Lab to Products Tests Whether Ecosystems Can Keep Up

Damo Academy said XuanTie processors have already been adopted in more than 200 mass-produced chips and nearly 1,000 mainstream terminal products—evidence that its RISC-V line has achieved volume presence in consumer and embedded markets. The C950 raises the bar: moving into servers requires not only silicon but stable toolchains, operating systems, and cloud-native software portability.

To accelerate that transition, Damo Academy highlighted its Flex scalable platform, offering modeling, verification environments and toolchains that allow chip design houses to customize XuanTie CPU implementations. It also pointed to its open-source work with the Institute of Software, Chinese Academy of Sciences , including the Ruyi community, where it said its kernel open-source contribution rate ranks first—an ecosystem metric relevant to data center adoption, where software maturity often determines time-to-deploy.

Industry participation expanded through the “Wujian Alliance” led by Damo Academy, which added members including Guoxin Tech, Canonical, China Telecom’s Tianyi Cloud and SGS, targeting SoC customization, operating system ecosystems, model-hardware integration and cloud deployment.

Anchoring in Shanghai Signals Policy-Backed Industrial Coordination

The Shanghai venue underscored how local policy and industrial clustering are shaping China’s RISC-V trajectory. Shanghai began supporting RISC-V in July 2018 and initiated the China RISC-V Industry Alliance that year, building a hub that combines research institutions, semiconductor supply chains and application demand.

Damo Academy tied key milestones to the city: the first-generation high-performance XuanTie C910 launch in 2019 as the first RISC-V CPU exceeding 2GHz; the 2020 release of the “Wujian 100” one-stop open-source design platform; and the return of the XuanTie RISC-V ecosystem conference to Shanghai in 2026. The implication for markets is that RISC-V’s next phase in China is being organized not only by corporate roadmaps but also by municipal coordination—potentially speeding standardization, talent flow and pilot deployments across cloud, telecom and industrial customers.

Looking ahead, Damo Academy said it will collaborate with the Beijing Open Source Chip Research Institute and the Institute of Software, Chinese Academy of Sciences on a next-generation open-source CPU—an effort that, if matched by broad software support, would further pressure proprietary instruction-set licensing models in targeted segments of China’s AI infrastructure.

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